数字电子技术复习

Purpose of the Course: The primary objective of this digital circuits course is to bridge the gap between human language and machine understanding. It aims to enable computers to comprehend and process information in a way that is analogous to human communication. Fundamentals of Digital Circuits:

• Logic Operations: The course begins with the mastery of logic operations, which are the building blocks of digital circuits. Understanding how these operations work is crucial for designing and analyzing digital systems.
• Combinational Logic Circuits: By combining logic operations, we create combinational logic circuits. These circuits produce outputs solely based on the current inputs, without any memory of past inputs.
• Sequential Logic Circuits: Introducing the concept of time into digital circuits leads to the creation of sequential logic circuits. These circuits not only consider the current inputs but also maintain a memory of past inputs, which allows for more complex operations and functionalities.
• Usage of the Study Material:
  • This material is a concise compilation of the knowledge points required for your exams. It is designed to provide you with a clear and focused overview of the essential concepts.
  • Understanding Circuits: For the diagrams and circuits presented, it is important to grasp their functions and applications. This will help you to not only memorize the components but also to apply them in practical scenarios.

Intro

• Analog quantity -- continuous values
• Digital quantity -- discrete set of values
• DAC: Digital $\to$ Analog
• ADC: Analog $\to$ Digital
• Bit: each of the two digits in the binary system
• Positive logic: high-1 low-0
• Negative logic: high-0 low-1
• A voltage in the unacceptable range can appear as either a HIGH or a LOW to a given circuit.
• Rising/Falling Leading/Trailing edge
• Pulse
• Waveform Charcteristics:
  • periodic / nonperiodic
  • Duty cycle: $(\frac{t_{w} }{T}) 100\%$
  • Frequency: $f=\frac{1}{T}$
  • period: $T=\frac{1}{f}$
• Each bit in a sequence occupies a defined time interval called a bit time.
• Data Transfer
  • Serial: one bit at a time along a single line
  • Parallel: all the bits in a group are sent out on separate lines at the same time.

Number Systems/Operations/Codes

$$(D)_{N}=\sum K_{i}\times N^i$$

• $N$ 是进制， $K_{i}$ 是第 $i$ 位的系数，等式另一端的 $N$ 是 $i$ 位的权重。
• Conversion of number systems
  • Division-by-2 / Multiplication-by-2 (for four significant digits)
• Binary arithmetic
  • 1's complement: changing all 1s to 0s and all 0s to 1s
  • 2's complement = 1's complement + 1
  • positive number 's complement is itself.
  • Sign Bit : 0-positive 1-negative
  • For signed numbers: add negative number = add 2's complement(or 1's complement + 1)
  • Range of Signed Integer Numbers: There is one less positive number than there are negative numbers because zero is represented as a positive number (all zeros).
• BCD Code
  • If a 4-bit sum is greater than 9, or if a carry out of the 4-bit group is generated, it is an invalid result. Add 6 (0110) to the 4-bit sum in order to skip the six invalid states and return the code to 8421
• Gray Code
  • B2G:
  • G2B：
  • Conclusion: add binary numbers
• Parity method for error detection
  • Explain
  • BCD codes
• Single-Precision Floating-Point Binary Numbers
  • Format:
  • Formula: Number $=(-1)^S(1+F)(2^{2^E-127})$
  • 0 is represented by all 0s
  • Infinity is represented by all 1s in the exponent and all 0s in the mantissa

Logic Gates and Boolean Algebra

• AND:
  • $A \cdot B \cdot C$
  • Logic signal:
• OR:
  • $A+B+C$
  • Logic signal:
• NOT:
  • $\overline{A}$
  • Logic signal:
• NAND: $F=\overline{A\cdot B \cdot C}$
• NOR: $F= \overline{A+B+C}$
• XOR
  • $F=A\oplus B$
  • Logic signal:
• XNOR (exclusive-NOR) : $F=\overline{A \oplus B}$
• DeMorgan's theorems
  • $\overline{A \cdot B}=\overline{A}+\overline{B}$
  • $\overline{A+B}=\overline{A}\cdot \overline{B}$
• SOP: Sum-of-product: $1010\to A \bar{B}C \bar{D}$
  • $m_{0}=\overline{A}\cdot \overline{B}$
• POS: Product-of-sum: $1001\to \bar{A}+B+C+\bar{D}$
  • $M_{0}=A+B$
  • $A+B=A+B+C \overline{C}$
• SOP→POS: $m_{1}+m_{3}+m_{6}+m_{7}=M_{0}M_{2}M_{4}M_{5}$
• Standard/minimum is different from each other.
• Karnaugh Map
  • 00/01/11/10
  • SOP → 1
  • POS → 0
  • Be careful that $m_{30}$ and $m_{28}$ is adjacent
• Others
  • Bubble: bubble appearing on the input/output → 0/LOW is the active or asserted input/output state.
  • Pin Numbering:
  • Performance Characteristics and Parameters
    • propagation delay time( $t_{p}$ ,the time interval between the transition of an input pulse and the occurrence of the resulting transition of the output pulse)
      • $t_{PHL}$ High to Low
      • $t_{PLH}$ Low to High
      • delays measured between the $50\%$ points of the corresponding edges of input/output
    • Power Dissipation($P_{D}$)
      • $P_{D}=V_{CC}\left( \frac{ {I_{C CH}+I_{C CL} } }{2} \right)$
    • SPP(Speed-Power Product)
      • $SPP=t_{p}P_{D}$
    • Fan out(for bipolar logic):maximum number of inputs of the same series in an IC family that can be connected to a gate's output and still maintain teh output voltage levels within specified limits.
      • specified in terms of unit loads
      • $Unit\ loads=\frac{I_{OL} }{I_{IL} }$

Combinational Logic

• Basic Combinational Logic Circuits
  • AND-OR Logic: $X=AB+CD$
  • AND-OR-Invert Logic: $X=\overline{AB+CD}$
  • Exclusive-OR Logic: $X=A \overline{B}+\overline{A}B=A\oplus B$
  • Exclusive-NOR Logic: $X=\overline{A} \ \overline{B}+AB$
• Dual operation

Functions

Half-Adder

$$C_{out}=AB$$ $$\sum=A\oplus B$$

$\sum$ is sum and $C_{out}$ is carry.

Full-Adder

$$C_{out}=AB+(A\oplus B)C_{in}$$ $$\sum=(A\oplus B)\oplus C_{in}$$

Parallel Binary Adders

• A group of four bits is called a nibble

Ripple Carry and Look-Ahead Carry Adders

• Reason: The speed with which an addition can be performed is limited by the time required for the carries to propagate, or ripple, through all the stages of a parallel adder.(Explainaiton:About Look-Ahead Carry Adders)
• Look-Ahead Carry Adders
  • Carry generation $C_{g}=AB$
  • Carry propagation $C_{p}=A+B$
  • $C_{out}=C_{g}+C_{p}C_{in}$
  • $\sum$ not changed

Comparators

Notice the comparator on the left has LOW input on the $A>B$ and $A<B$ , and HIGH input on the $A=B$ .

Encoder

Priority Encoder

• ignore any other lower-order active inputs
• $F_{0}=I_{7}+\overline{I_{7} }I_{5}+\overline{I_{7} }\ \overline{I_{5} }I_{3}+\overline{I_{7} }\ \overline{I_{5} }\ \overline{I_{3} }I_{1}$
• 16-4 priority encoder

Decoders

74HC154

When $\overline{CS_{1} }$ and $\overline{CS_{2} }$ is HIGH, the $EN$ is activated.

BCD/7-seg

• Lamp Test:
  • LOW: $\overline{LT}$ (input)
  • HIGH: $\overline{BI} / \overline{RBO}$ (output)
  • seven segment in the display are turned on
• Zero Supression
  • $030.080\to 30.08$
  • $\overline{BI}/\overline{BRO}$ share the same pin.
  • When $\overline{RBI}$ is LOW and BCD inputs is zero code, all of the segment outputs of the decoder are nonactive(HIGH),and $\overline{RBO}$ is LOW.
  • Supression's $BI/RBO$ $\to$ Next's $RBI$ (十位数，从左到右；分数，从右到左)
• $\overline{BI}$ is LOW, all segment outputs are nonactive(HIGH)

Code Converters

BCD-to-Binary

Binary-to-Gray / Gray-to-Binary

• B2G
• G2B

Multiplexers

8-to-16

7-seg display multiplexer

Logic Function Generator

DeMux

Parity generators/checkers

Generators

Checker

Latches, Filp-Flops, and Timers

Latches

Active-High S-R Latch

$R$	$S$	$Q^{n+1}$
0	0	$Q^{n}$	Remains
1	0	0	Reset
0	1	1	Set
1	1	$0^*$	Invalid（0）

$$Q^{n+1}=S+\bar{R}Q^n$$ $$S\cdot R=0$$

• $EN$ is HIGH, the output in controlled by the state of S and R; $EN$ is LOW, the output is not affected(stay same)
• Application: Contact-Bounce Eliminator

D Latch

• When $EN$ is 0, $Q$ stay the same
• When $EN$ is 1, $Q^{n+1}=D$

Flip-Flops

• Latch/Flip-Flops: Flip-Flops has CLK, Latch only have $EN$

Master-Slave Flip-Flops

• 下降沿状态（如果为0/0），就往前追溯

Edge-triggered flip-flop

$$Q^{n+1}=J \bar{Q}^n+\bar{K}Q^n$$

• $\overline{PRE}$ set 1; $\overline{CLR}$ set 0
• Edge-Triggered Operation

Operating Characteristics

• Propagation Delay Times
  • $t_{PLH}$
  • $t_{PHL}$
• Set-up Time $t_{s}$
  • minimum interval required for the logic levels to be maintained constantly on the inputs
• Hold Time $t_{h}$
  • minimum interval required for the logic levels to remain on the inputs after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.
• Maximum Clock Frequency $f_{max}$
  • highest rate at which a flip-flop can be reliably triggered
• Pulse Widths $t_{w}$

Application

• Parallel Data Storage
• Frequency Division
  • $n$ is the number of flip-flops, a frequency division of $2^n$ is achieved.important
• counting

One-shots

• Nonretriggerable
  • 
  • $t_{w}=RC\ln{2}\approx 0.7RC$
• Retriggerable
  • $t_{w}=0.32RC\left( 1+\frac{0.7}{R} \right)$
• Can use some one-shots to make a sequential timing circuit

555 timer

One-Shot Operation

• $t_{p}$ : $u_{C_{1} }(t)=V_{CC}-V_{CC}e^{ -t/R_{1}C_{1} }$
  • $\frac{2V_{CC} }{3}=V_{CC}(1-e^{ -t_{p}/R_{1}C_{1} })$
  • $t_{p}=R_{1}C_{1}\ln3 \approx1.1R_{1}C_{1}$

Schmitt trigger

• $u_{i}> \frac{2}{3}V_{CC}$ , RESET, $u_{o}$ is HIGH
• $u_{i}< \frac{1}{3}V_{CC}$ , SET, $u_{o}$ is LOW

The Astable Multivibrator

• $v_{in}$ reach $UTP$ , $v_{out}$ goes LOW; $v_{in}$ reach $LTP$ , $v_{out}$ goes HIGH

• 

• Charge: $t_{H}=(R_{1}+R_{2})C\ln2\approx 0.7(R_{1}+R_{2})C_{1}$ ($\frac{2}{3}V_{CC}=V_{CC}-\frac{2}{3}V_{CC}e^{ -t/RC }$)

• Discharge: $t_{L}=0.7R_{2}C_{1}$ ($\frac{1}{3}V_{CC}=\frac{2}{3}V_{CC}e^{ -t/RC }$)

• $T=0.7(R_{1}+2R_{2})C_{1}$

• $f=\frac{1.44}{(R_{1}+2R_{2})C_{1} }$

• $Duty \ cycle=\left( \frac{ {R_{1}+R_{2} }}{R_{1}+2R_{2} } \right)100\%$

• 如果 $out$ 那边接了东西：$P=\frac{v^2}{R} \frac{t_{H} }{t_{H}+t_{R} }$

Achieve duty cycles less than 50%

• $Duty\ cycle=\left( \frac{R_{1} }{R_{1}+R_{2} } \right)100\%$

Counters

• Finate State Machines
  • Moore machine: Outputs only depend on the current state.
  • Mealy machine: Output depend on current state and inputs.
• Asynchronous / Synchronous
  • Asynchronous: because of the inhernet propagation delay time through a flip-flop(or other), the flip-flops are never simultaneously triggered.
    • Decade Counters: 1010 $\to$ 0000, producing a glitch(a false or spurious electronic signal)
    • Propagation Delay
    • $n$ Bit asynchronous binary counter, propagation delay $t_{p}$ , $f_{max}=\frac{1}{T_{min} }=\frac{1}{nt_{p} }$
  • Synchronous: with a same CLK
    • Decade Counters: 1001 $\to$ 0000
    • 74HC163:
      • $\overline{CLR}$ : resets all four flip-flops(+ $CLK$ synchronous)
      • $\overline{LOAD}$ : assume the state of the data inputs(+ $CLK$)
      • $ENP$ / $ENT$ (or called $TC$ (terminal count)): both HIGH for sequence through; at least one input LOW, counter disabled.
      • $RCO$ goes HIGH, when counter reaches the last state(terminal count)
    • 74HC160
      • $\overline{CLR}$ : asynchronous
    • UP/DOWN Synchronous Counters(74HC190)
      • $MAX / MIN$ : produces HIGH pulse when reach max/min number
      • $\overline{CTEN}$ : count enable

Cascaded Counters

• modulus: multiple all the modulue
• Truncated Sequences $N\to M \ and \ N>M$ :
  • Set zero:
    • Synchronous: $S_{M-1}$
    • Asynchronous: $S_{M}$
  • Set number:
    • Synchronous: jump over $N-M$ states
    • Asynchronous: jump over $N-M+1$
  • 
• decoding glitches:
  • using strobing

Design of a state machine

• Transition table for a J-K filp-flop

$Q^n$	$Q^{n+1}$	$J$	$K$
0	0	0	X
0	1	1	X
1	0	X	1
1	1	X	0

• Model of a Sequential Circuit:
• Excitation Equation: $J=……$
• Equation of JK/D/etc.
• State Equation(add these two together $Q_{0}=……$)
• Output equation: $Y=……$

提示

• 注意是否有小圆圈
• dual 对偶
• 分清 encoder 和 decoder
• 注意 state diagram 里面 $Q_{0}Q_{1}$ 的顺序
• LSB--least significant bit
• bistable 双稳态
• monostable 单稳态
• astable multivibrator 非稳态多谐振荡器
• Flip-flops and latches are both bistable devices.
• 计数器记得算0